1. Field
One aspect of the present invention relates to a cache control apparatus for controlling data transmission between a CPU and a memory, an information processing apparatus provided with the cache control apparatus, and a cache control method.
2. Description of the Related Art
In recent years, the operating frequency of an LSI is being increased remarkably and, as a result, memory access time is relatively larger than the processing time in the LSI.
As a countermeasure against the above problem, there is performed a speculative fetch in which a system controller (hereinafter, referred to as “SC”) that receives a memory fetch request from a CPU or an I/O controller issues a memory fetch request to a memory controller (hereinafter, referred to as “MAC”) before it becomes clear whether requested data is stored or not in a cache of the CPU.
That is, the SC retains inside thereof tag information of data, such as address or update state, stored in the cache of every CPU and searches (snooping) for the tag information to perform a speculative memory access at a stage before it becomes clear whether data requested in a memory fetch request is stored or not in the cache of the CPU. The speculative fetch allows an early start of the memory access operation, thereby reduces a memory access waiting time, latency in other words, if the data does not exist in the cache.
There have been known methods for reducing the memory access latency. For example, a method that speculatively accesses a memory in a system in parallel with reading out from a tag memory, tag information which is information concerning a data storage state of a cache memory provided in the system and determines whether to discard or not data acquired from the memory by the speculative reading based on the read out tag information have been known. Further, there is known a mechanism that retains response data corresponding to a speculative fetch in a given location in a system so as to wait for a result of cache search made by a CPU, based on which it is determined whether to adopt or not the response data corresponding to the speculative fetch and a method that processes a speculative request so that convergence and collision due to non-speculative traffic are reduced
There are several related arts discussing on the speculative fetch.    Patent Document 1: Jpn. Pat. Appln. Laid-Open Publication No. 2001-167077.    Patent Document 2: Jpn. Pat. Appln. Laid-Open Publication No. 2003-186669.
In the case where a conventional speculative fetching method is applied to a system including a memory control apparatus that gives preference to a fetch command having a smaller packet length over a command having a longer packet length, such as an STR (Store: command of writing data in a memory), when a fetch request and an STR request for the same address conflict with each other (access requests are made to the same address), ordering between requests exchanged in the system cannot be maintained.
With reference to FIGS. 5A and 5B each showing a timing at which the speculative fetch is transmitted after the STR command has been made, a further description of the ordering between requests will be given. Note that FIG. 5A shows a successful example of the speculative fetch, and FIG. 5B shows a failed example thereof. In FIGS. 5A and 5B, the horizontal axis represents time.
When the STR command is issued from the CPU, the SC notifies the MAC of the STR command to thereby update data in the memory (transition from OLDDATA to NEWDATA in MAC).
In the case of FIG. 5A, data has already been updated at the time point when the speculative fetch is issued and reaches the MAC, so that the data acquired by the speculative fetch can be adopted without problems.
On the other hand, in the case of FIG. 5B, unupdated data (OLDDATA) before STR is read out although NEWDATA should be readout under normal circumstance. Thus, when the data acquired by the speculative fetch is adopted, a problem arises.
Further, in the above method that retains data acquired by the speculative fetch in the system, it is necessary to temporarily store the acquired data in a buffer in the SC and wait for a snoop result before determining whether to adopt or not the response data corresponding to the speculative fetch. Thus, the buffer size needs to be increased, which unfavorably results in an increase in the LSI size and power consumption.
Further, when the speculative fetch results in failure, bus throughput is lowered accordingly. Therefore, it is necessary to reduce the number of times of failure in the speculative fetch as much as possible.